下午在看用Host (PC)寫 EC的 flash Code, 查了一點資料, 主要是 Port 60h/64h/62h/66h 有關
Port 60h : data register for KBC
Port 64h : command/status register for KBC, write a command to the IO port/read a status from the IO port
Port 62h : data register for EC (EC_DATA)
Port 66h : command/status register for EC(EC_SC)
當然要如何寫入 EC 的 Flash 那就須要定出一個溝通的Protocol, 這部份好像沒有標準依循, 不過EC應該都是8051 Base
除了定址空間外, 當初是INTEL 主導ACPI Spec. 所以理所當然用 8051 做 EC controller 的Core, 至少個人目前用Google找的EC Controller 還沒看到有不同Core的EC。(Update:有看到Winbond 有作RISC 16bits core的 EC/KBC controller license by National Semicondtor and Hitachi H8 Core at Sep. 28 2008)
而ACPI 已經定的標準 EC Command 共有下列 5個 (ref. Chapter 12 of ACPI 3.0b Spec.)
- 0x80, RD_EC, Read Embedded Controller, 讀取EC的記憶體空間的資料
- 0x81, WR_EC, Write Embedded Controller, 寫入資料到EC的記憶體空間
- 0x82, BE_EC, Burst Enable Embedded Controller
- 0x83, BD_EC, Burst Disable Embedded Controller
- 0x84, QU_EC, Query Embedded Controller
PC Architecture Legacy Standard I/O Port
60h/64h : KBC, Keyboard Controller
62h/66h: ACPI EC0 (Embedded Controller 0)
92h, Fast GateA20 and Keyboard Reset
3F0h ~ 3F7h, FD0, Floopy Device 0
370h ~ 377h, FD1, Floopy Device 1
CF8h/CFCh, PCI configuration address/data port
ref. Table 25: Legacy Host Decode Ranges, Intel LPC(Low Pin Count) https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf (backup)
// page 319, ACPI 3.0b Spec.
Device (EC0) {
Name (_HID, EISAID(“PNP0C09″))
Name (_CRS,
ResourceTemplate () { // port 0x62 and 0x66
IO (Decode16, 0x62, 0x62, 0, 1),
IO (Decode16, 0x66, 0x66, 0, 1)
}
)
Name (_GPE, 0)
Device (SMB0) {
Name (_HID, “ACPI0001″) // Smart Battery Host Controller
Name (_EC, 0x8030) // EC offset (0x80), Query (0x30)
Device (SBS0){ // Smart Battery Subsystem
Name (_HID, “ACPI0002″) // Smart Battery Subsystem ID
Name(_SBS, 0x1) // Indicates support for one battery
} // end of SBS0
} // end of SMB0
} // end of EC
額外的感想 8051 感覺路好寬呀 XD
常見的有CD/DVD ROM/OSD(TV/Monitor)/PC 上面的EC 都需要人maintain, 真是怪了以前找工作怎麼都沒人要我 T_T
願~~ 